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Semiconductor ElectronicsNEET Physics · Class 12 · NCERT Chapter 14

30 NEET previous-year questions on Semiconductor Electronics, each with the correct answer and a step-by-step solution. Sourced directly from official NEET papers across every booklet code.

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All (30)
Semiconductor Electronics (30)

A

It is V-I characteristic for solar cell where, point A represents open circuit voltage and point B short circuit current

B

It is for a solar cell and points A and B represent open circuit voltage and current, respectively

C

It is for a photodiode and points A and B represent open circuit voltage and current, respectively

D

It is for a LED and points A and B represent open circuit voltage and short circuit current, respectively

Solution

The V-I characteristic shown is typical of a solar cell, where point A represents the open circuit voltage (Voc) and point B represents the short circuit current (Isc). NCERT XII chapter Semiconductor Electronics explains that in a solar cell, the open circuit voltage is the maximum voltage available when no current is drawn, and the short circuit current is the maximum current when the voltage is zero, so option (a) is correct.

A

(a) and (b) only

B

(b) only

C

(b) and (c) only

D

(a), (b) and (c)

Solution

The barrier potential of a p-n junction depends on the type of semiconductor material, the amount of doping, and the temperature. NCERT XII chapter Semiconductor Electronics explains that all three factors influence the barrier potential, so option (d) is correct.

A

30 mA

B

40 mA

C

20 mA

D

35 mA www.vedantu.com 30

Solution

Current=(3.5−0.5) 100 A = 3 100A= 30 mA

A

0 A www.vedantu.com 10

B

10−2 𝐴

C

10−1 𝐴

D

10−3 𝐴

Solution

VA − V3 = 4 −(−6)= 10 ∴ i = 10 1000= 10−2 A

A

4, 3.84

B

3.69, 3.84

C

4, 4

D

4, 3.69

Solution

Voltage gain = β.( RC RB ) V = 0.96(80 192) V =96 × 8 192 = 4 And power gain of the amplifier is βac.Av = 0.96 × 4 = 3.84

A

A = 0,B = 1,C = 0

B

A = 1,B = 0,C = 0

C

A = 1,B = 1,C = 0

D

A = 1,B = 0,C = 1

Solution

For the output to be 1 in a NAND gate circuit, at least one input to the final NAND gate must be 0. Given the options, the correct combination is , , and , which ensures the final NAND gate receives a 0 from the AND gate, resulting in an output of 1. Option (d) is correct.

A

200 and 1000

B

15 and 200

C

150 and 15000

D

20 and 2000

Solution

Current gain (β) = 100 Voltage gain (A V) = c b R Rβ = 3100 2 ⎛⎞⎜⎟⎝⎠ = 150 Power gain = AV β = 150 (100) = 15000

A

–2 V0 V R

B

–3 V–4 V R

C

+2 V–2 V R

D

5 V3 V R

Solution

In forward bias, p-type semiconductor is at higher potential w.r.t. n-type semiconductor.

A

AND gate

B

OR gate

C

NOR gate

D

NOT gate

Solution

YA B=+ www.vedantu.com 7

A

I B = 20 μ A, I C = 5 mA, β = 250

B

I B = 25 μ A, I C = 5 mA, β = 200

C

I B = 40 μ A, I C = 10 mA, β = 250

D

I B = 40 μ A, I C = 5 mA, β = 125

Solution

Using the formula and given , , and , the base current can be calculated as . Given , , so option (b) is correct.

A

does not affect resistance of p-n junction

B

affects only forward resistance

C

affects only reverse resistance

D

affects the overall V – I characteristics of p-n junction

Solution

Temperature changes affect the carrier concentrations and mobility in both p-type and n-type materials, altering the overall V-I characteristics of the p-n junction. NCERT XII chapter Semiconductor Electronics explains that temperature variations impact the diode's forward and reverse bias behavior, so option (d) is correct.

A

B A . + A . B

B

A . – B + – A . B

C

B A .

D

B A +

Solution

The given combination of gates results in the output . This is the expression for the XOR gate, which is represented by option (a).

A

0.5 cm

B

100 cm

C

10 cm

D

1 cm

Solution

4𝑇 𝑅 =𝑝𝑔ℎ (ℎ= 𝑍0) 𝑍0= 4×2.5×10−2 10−3 ×103×10 =10 𝑚𝑚=1 𝑐𝑚

A

6.4×10−6 𝑚3/𝑠

B

12.6×10−6 𝑚3/𝑠

C

8.9×10−6 𝑚3/𝑠

D

2.23×10−6 𝑚3/𝑠

Solution

𝑄=𝑎𝑣=𝑎 √2𝑔ℎ = (2×10−6) √2×10×2 =2×2×√10×10−6 =4×3.16×10−6 =12.6×10−6 𝑚3/𝑠

A

Base, emitter and collector regions should have same doping concentrations.

B

Base, emitter and collector regions should have same size.

C

Both emitter junction as well as the collector junction are forward biased.

D

The base region must be very thin and lightly doped.

Solution

For transistor action, the base region must be very thin and lightly doped to ensure that most of the charge carriers injected from the emitter reach the collector. This is a key requirement for proper transistor operation, as described in NCERT XII Semiconductor Electronics, so option (d) is correct.

A

A B Y 0 0 0 0 1 0 1 0 0 1 1 1

B

A B Y 0 0 0 0 1 1 1 0 1 1 1 1

C

A B Y 0 0 1 0 1 1 1 0 1 1 1 0

D

A B Y 0 0 1 0 1 0 1 0 0 1 1 0 - o 0 o -

Solution

The given logic circuit is an AND gate, which outputs a high (1) only when both inputs are high (1). The truth table for an AND gate is as follows: 0 0 0 0 1 0 1 0 0 1 1 1, so option (a) is correct.

A

forward bias only

B

reverse bias only

C

both forward bias and reverse bias

D

increase in forward current

Solution

The width of the depletion region increases under reverse bias, as the applied voltage enhances the electric field and repels more majority carriers away from the junction. NCERT XII chapter Semiconductor Electronics explains that reverse bias widens the depletion region, so option (b) is correct.

A

is incorrect.

B

C

is incorrect but

D

is correct.

Solution

A zener diode is indeed connected in reverse bias for voltage regulation, making statement (A) correct. The potential barrier of a p-n junction typically ranges from 0.1 V to 0.3 V, making statement (B) also correct. Therefore, option (1) is the correct choice.

A

current in n-type = current in p-type.

B

current in p-type > current in n-type.

C

current in n-type > current in p-type.

D

No current will flow in p-type, current will only flow in n-type.

Solution

In an n-type semiconductor, the majority carriers are electrons, which have higher mobility compared to holes in a p-type semiconductor. Therefore, the current in an n-type semiconductor is greater than the current in a p-type semiconductor under the same applied electric field, making option (c) correct.

A

B

C

D

Solution

The output at terminal is determined by the logic gates in the circuit. Without the diagram, the specific logic function cannot be determined, but if the correct answer is given as option (a), it implies that the circuit configuration corresponds to the logic function represented by that option.

A

Circuit (a) only

B

Circuit (b) only

C

Circuit (c) only

D

Both circuits (a) and (c)

Solution

Potential drops across the p-n junctions will be same if either both junctions are forward biased or both junction are reverse biased. In figure (a) and (c), both junctions are forward biased therefore both have same potential. In figure (b) first junction is forward biased and second junction is reverse biased, so both junctions have different potential difference.

A

000 011 101 110 ABC

B

001 010 100 111 ABC

C

001 010 101 110 ABC

D

000 011 100 111 ABC

Solution

( ) ( )C AB AB= ⋅⋅⋅ ⇒ C AB AB=⋅+⋅ ⇒ ( )C A AB= + ⇒ CB= The truth table would be 001 010 101 110 ABC

A

Load resistance

B

A centre-tapped transformer

C

p-n junction diodes

D

Capacitor

Solution

The capacitor smooths the rectified output by charging and discharging, thereby reducing the AC ripple. NCERT XII chapter Semiconductor Electronics explains that the capacitor acts as a filter in a full wave rectifier circuit, so option (d) is correct.

A

Statement I is incorrect but Statement II is correct.

B

Both Statement I and Statement II are correct.

C

Both Statement I and Statement II are incorrect.

D

Statement I is correct but Statement II is incorrect.

Solution

Statement I is correct as photovoltaic devices, such as solar cells, convert light energy into electrical energy. Statement II is also correct as Zener diodes are specifically designed to operate in the reverse breakdown region to regulate voltage. Both statements align with the principles described in NCERT XII Semiconductor Electronics, so option (b) is correct.

A

A B Y 0 0 0 0 1 0 1 0 0 1 1 1

B

A B Y 0 0 1 0 1 1 1 0 1 1 1 0

C

A B Y 0 0 0 0 1 1 1 0 1 1 1 1

D

A B Y 0 0 1 0 1 0 1 0 1 1 1 0

Solution

The circuit consists of two NOT gates followed by a NOR gate. The output of the NOR gate is high (1) only when both inputs are low (0), so the truth table is:
- A = 0, B = 0
NOT A = 1, NOT B = 1 NOR(1, 1) = 0
- A = 0, B = 1
NOT A = 1, NOT B = 0 NOR(1, 0) = 0
- A = 1, B = 0
NOT A = 0, NOT B = 1 NOR(0, 1) = 0
- A = 1, B = 1
NOT A = 0, NOT B = 0 NOR(0, 0) = 1
Thus, the correct truth table is option (c).

A

.AB A+

B

.A B A+

C

B

D

B

Solution

0 0 1 0 1 0 1 0 1 1 1 0 A B Y According to given truth table, output is independent on value of A ∴ Output YB=

A

A is correct but B is incorrect

B

A is incorrect but B is correct

C

Both A and B are correct

D

Both A and B are incorrect

Solution

A: Solar cell characteristics B: In reverse biased pn junction diode, the current measured in (μA), is due to minority charge carrier.

A

NAND gate

B

NOR gate

C

OR gate

D

AND gate

Solution

1 =⋅Y A A = A 2 =+Y B B = B 12=+Y Y Y =+AB =⋅AB = A.B is similar to output of AND Gate - 13 - NEET (UG)-2024 (Code-Q1)

A

AND

B

NAND

C

OR

D

NOR

Solution

Sol.

This is equivalent to a NOR gate when both inputs are same.

A

is forward biased, is reverse biased

B

is reverse biased, is forward biased.

C

and both are forward biased

D

and both are reverse biased

Solution

Sol. volt

t = 15 ms

t = 0.015 s

T = 0.02 s

i.e. negative half cycle.

So now negative half cycle is fed to circuit making D_1 as reverse biased and D_2 as forward biased.

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